The present invention relates to a delay locked loop (DLL) and a method of driving the same, and more particularly, to a delay locked loop (DLL) and a method of driving the same, which can reduce power consumption.
In general, a clock in the system or the circuit is used as a reference for matching the operating timing. The clock is also used to secure much faster operation without error. When the clock externally inputted is used internally, time delay (clock skew) by the internal circuit occurs. In order to compensate for such time delay and thus make the internal clock have the same phase as the external clock, a delay locked loop (DLL) is used.
Meanwhile, the DLL has the advantage that it is less sensitive to noise than the phase locked loop (PLL) that has been conventionally used. For this reason, the DLL has been widely used for a synchronous semiconductor memory including DDR SDRAM (double data rate synchronous DRAM). Of them, a register controlled DLL has been widely utilized.
As the time taken to exit an active power down mode is tCD, it can sufficiently satisfy active power down excitation time rules.
The clock outputted from the DLL is used only when the DRAM receives the read command. In other words, if the read command is not applied, the DLL continues to perform a locking operation. Actually, the output of the DLL is not at all used.
From the DDR II SDRAM, the power down mode is classified into two types in which the power down excitation time is differently specified for each of the two types. In other words, the power down mode is classified into an active power down mode and a precharge power down mode. As the active power down mode bank is active, the read operation can be performed directly after power-down excitation. On the contrary, after the precharge power down mode is excited, the active command is applied to activate the bank and the read operation is then performed. Therefore, a certain time is taken in using the output of the DLL. For this reason, in the DDR II SDRAM rules, the active power down excitation time is 2 cycles but the precharge down excitation time is 6 cycles.
The DLL used in the conventional synchronous DRAM will now be described with reference to FIG. 1.
A clock buffer 10 for buffering an external clock CLK to generate an internal clock CLKin is provided. The internal clock CLKin is delayed in a delayed line 20 for a certain time and is then inputted to a clock driver 30. The clock driver 30 buffers the internal clock CLKin delayed in the delayed line 20 to generate a clock signal CLKout.
A delayed monitor 60 having the same delay path as the external clock CLK is provided. The clock signal CLKout is delayed in the delayed monitor 60 and is then inputted to a phase detector 40. The phase detector 40 detects the difference in a phase between the clock signal CLKout via the delayed monitor 60 and the internal clock CLKin to generate shift control signals shift-left and shift-right. A shift register 50 determines a delay time of the delayed line 20 according to the shift control signals shift-left and shift-right. In other words, if the shift control signal shift-left is inputted to the shift register 50, the register moves left. On the contrary, if the shift control signal shift-right is inputted to the shift register 50, the register moves right. Delay is fixed at the time when the clock signal CLKout via the delayed monitor 60 and the internal clock CLKin have the minimum jitter.
In the DDR or DDR II SDRAM to which such a DLL is applied, however, the DLL is entirely operated regardless of the power down mode to consume the current. Due to this, lots of the power is consumed. This reason will be described as follows.
In the DDR or DDR II SDRAM, as the active power down excitation time (time taken to exit from the power down mode to the normal mode) is very short, about 2 cycles, the DLL cannot be completely turned off even in the active power down mode. In other words, if it is required that a DLL clock be outputted after the DLL is completely turned off during the active power down mode, the active power down mode has to pass through the clock buffer 10, the delayed line 20 and the clock driver 30, as described above. Assuming that the delay time of the clock buffer 10 is tCB, the delay time of the delayed line 20 is tDL and the delay time of the clock driver 30 is tCD, tCB+tDL+tCD is significantly higher than the power down excitation time (about 2 cycles). Therefore, in the prior art, lots of the power is consumed since the DLL is entirely operated even in the active power down mode.
An object of the present invention is to provide a delay locked loop (DLL) and a method of driving the same capable of solving the aforementioned problems.
Another object of the present invention is to provide a delay locked loop (DLL) and a method of driving the same, which can satisfy the active power down excitation time while reducing power consumption, by partially turning off the DLL while keeping locking information of the DLL itself during the active power down mode.
According to one aspect of the present invention for achieving the object, there is provided a delay locked loop, including a clock buffer for buffering an inputted external clock to generate an internal clock, the clock buffer generating a control signal for disabling the internal clock depending on whether the power is down, a delayed line for delaying the internal clock, a clock driver for buffering the output of the delayed line to generate a clock signal, the clock driver disabling the clock signal depending on whether the power is down, a delay monitor for delaying the external clock, a phase detector for detecting the difference in a phase between the internal clock and the output of the delayed monitor to generate a detected signal, the phase detector being disabled according to the control signal, and a shift register for controlling the delayed line according to the detected signal from the phase detector.
According to another aspect of the present invention, there is provided a method of driving a delay locked loop, including the steps of in an active power down mode, disabling the phase detector, the shift register and the clock driver, while keeping an enable state of the clock buffer and the delayed line, at the time of active power down excitation, enabling the disabled phase detector, the shift register and the clock driver, in a precharge power down mode, disabling the clock buffer, the delayed line, the clock driver, the delayed monitor, the phase detector and the shift register, and at the time of precharge power down excitation, enabling the clock buffer, the delayed line, the clock driver, the delayed monitor, the phase detector and the shift register.